1. Field
An aspect of the present invention relates to computer circuit design.
2. Description of the Related Art
Conventionally, development of printed boards is performed according to a development flow as shown in FIG. 1A. There is an application for circuit design used in “circuit design” and the like in this development flow (see FIG. 1B).
The application for circuit design is provided with a design rule check mechanism (see Japanese Laid-open Patent Publication No. H10-240789).
The design rule check mechanism is a mechanism which checks for errors with respect to check items, for example, checks if characters do not overlap with graphics, checks if an input pin and an output pin are used, etc. in a circuit diagram in which a circuit is drawn, and issues a warning to a user when an error is detected (see FIG. 1C).
For avoiding a troublesome situation where warnings are repeatedly issued with respect to the same error, the design rule check mechanism has an “allowance setting” for suspending issue of warning.
In one specific example, a circuit designing device (for example, a CAD (Computer Aided Design) device) having an application for circuit design stores an error ID which identifies a respective error in association with error allowance information which allows issue of warning to be prevented.
If a user checks an error description on receipt of a warning and inputs a command intended to suspend issue of warning about this error, the error allowance information is switched from “Not OK” indicating the error causes issue of warning to “OK” indicating the error does not cause issue of warning.
During execution of design rule check, the circuit designing device checks error allowance information stored in association with an error ID, and if the error allowance information is stored as “Not OK”, issues a warning, and if it is stored as “OK”, suspends issue of warning (see FIG. 1D). It is noted that FIGS. 1C, and 1D are diagrams showing an overview of the conventional art.